15.3.9 PLL Control Register
Note:
- The number of external clock fail detection modules is device-dependent.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PLLxCON |
| Offset: | 0x3180, 0x318C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CLKRDY | PLLSWEN | RIS | FOUTSWEN | EXTCFEN | EXTCFSEL[2:0] | ||||
| Access | R/HS/HC | R/S/HC | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OSWEN | DIVSWEN | FSCMEN | BOSC[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | OE | NOSC[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COSC[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 31 – CLKRDY Output Clock is Ready bit
| Value | Description |
|---|---|
| 1 | Clock output is ready |
| 0 |
Clock output is not ready, may be due to source clock not ready, source selection change is in progress, divider change is in progress, or a clock failure has been detected and the backup clock has not yet occurred |
Bit 30 – PLLSWEN PLL Input and Feedback Divider Switch Enabled bit
| Value | Description |
|---|---|
| 1 | Enable PLL input and feedback divider update |
| 0 | Divider Switch has completed |
Bit 29 – RIS Run In Sleep bit
| Value | Description |
|---|---|
| 1 | PLL block will continue to operate if SLEEP mode is entered |
| 0 | PLL block will stop when SLEEP mode is entered |
Bit 28 – FOUTSWEN Clock Divider Switch Enabled bit
| Value | Description |
|---|---|
| 1 | Enable PLL output divider update |
| 0 | Divider switch has completed |
Bit 27 – EXTCFEN External Clock Fail Event Enable bit
| Value | Description |
|---|---|
| 1 | External clock fail detection is enabled |
| 0 | External clock fail detection is disabled |
Bits 26:24 – EXTCFSEL[2:0] External Clock Fail Event Select bits(1)
| Value | Description |
|---|---|
| 0011 | External clock fail detection module #4 |
| 0010 | External clock fail detection module #3 |
| 0001 | |
| 0000 | External clock fail detection module #1 |
Bit 23 – OSWEN Oscillator Switch Enable bit
| Value | Description |
|---|---|
| 1 | Request oscillator switch to selection specified by NOSC[3:0] bits |
| 0 | Oscillator switch is complete |
Bit 22 – DIVSWEN Clock RODIV/ROTRIM Switch Enable bit
| Value | Description |
|---|---|
| 1 | Clock Divider Switching currently in progress |
| 0 | Clock Divider Switching has completed |
Bit 20 – FSCMEN Fail-Safe Clock Monitor Enable bit
| Value | Description |
|---|---|
| 1 | Fail-Safe Clock Monitor is enabled |
| 0 | Fail-Safe Clock Monitor is disabled |
Bits 19:16 – BOSC[3:0] Backup Reference Clock Select bits
Bit 15 – ON Enable PLL Generator bit
| Value | Description |
|---|---|
| 1 | PLL Generator is enabled |
| 0 | PLL Generator is disabled |
Bit 13 – SIDL Stop in Idle bit
| Value | Description |
|---|---|
| 1 | Clock Generator block will stop when IDLE mode is entered |
| 0 | Clock Generator block will continue to operate when IDLE mode is entered |
Bit 12 – OE Output Enable bit
| Value | Description |
|---|---|
| 1 | Clock output is enabled to be output on a device pin |
| 0 | Clock output on a pin is disabled |