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15.3.17 Clock Monitor Input
Selection Register
Table 15-22. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: CMxSEL Offset: 0x320C, 0x323C,
0x326C, 0x329C
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 CNTSEL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bit 7 6 5 4 3 2 1 0 WINSEL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bits 15:8 – CNTSEL[7:0] Counter clock
source Selects the
monitored clock source. See Table 15-5 Bits 7:0 – WINSEL[7:0] Window clock
source
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