8.2.172 GMAC Express EMAC Receive Status Register

This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a one to them. It is not possible to set a bit to 1 by writing to the register.

Name: GMAC_EMAC_RSR
Offset: 0x1020
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   RXDMALCKRXMACLCKHNORXOVRRECBNA 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 5 – RXDMALCK Receive DMA Lockup (Clear by Writing a 1)

Set when lockup has been detected on the DMA receive path. Writing a one clears this bit.

Bit 4 – RXMACLCK Receive MAC Lockup (Clear by Writing a 1)

Set when lockup has been detected on the MAC receive path. Writing a one clears this bit.

Bit 3 – HNO System Bus Error (Clear by Writing a 1)

Set when the DMA block sees a system bus error. Writing a one clears this bit.

Bit 2 – RXOVR Receive Overrun (Clear by Writing a 1)

This bit is set if the receive status was not taken at the end of the frame. This bit is also set if the packet buffer overflows. The buffer will be recovered if an overrun occurs. Writing a one clears this bit.

Bit 1 – REC Frame Received (Clear by Writing a 1)

One or more frames have been received and placed in memory. Writing a one clears this bit.

Bit 0 – BNA Buffer Not Available (Clear by Writing a 1)

An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will re-read the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Writing a one clears this bit.