8.2.22 GMAC Lockup Configuration Register
| Name: | GMAC_LCKUP_CFGR |
| Offset: | 0x068 |
| Reset: | 0x07FFFFFF |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TXDMA_LCKUP_EN | TXMAC_LCKUP_EN | RXDMA_LCKUP_EN | RXMAC_LCKUP_EN | LCKUP_REC_EN | DMA_LOCKUP_TIME[10:8] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DMA_LOCKUP_TIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRESCALER[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRESCALER[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 31 – TXDMA_LCKUP_EN Transmit DMA Lockup Detector Enable
| Value | Description |
|---|---|
| 0 | Disables the monitor that detects lockups in the transmit DMA. |
| 1 | Enables the monitor that detects lockups in the transmit DMA. |
Bit 30 – TXMAC_LCKUP_EN Transmit MAC Lockup Detector Enable
| Value | Description |
|---|---|
| 0 | Disables the monitor that detects lockups in the transmit MAC. |
| 1 | Enables the monitor that detects lockups in the transmit MAC. |
Bit 29 – RXDMA_LCKUP_EN Receive DMA Lockup Detector Enable
| Value | Description |
|---|---|
| 0 | Disables the monitor that detects lockups in the receive DMA. |
| 1 | Enables the monitor that detects lockups in the receive DMA. |
Bit 28 – RXMAC_LCKUP_EN Receive MAC Lockup Detector Enable
| Value | Description |
|---|---|
| 0 | Disables the monitor that detects lockups in the receive MAC. |
| 1 | Enables the monitor that detects lockups in the receive MAC. |
Bit 27 – LCKUP_REC_EN Lockup Recovery Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Forces the MAC in Reset mode when a lockup is detected on the transmit or receive data paths. |
Bits 26:16 – DMA_LOCKUP_TIME[10:0] Timeout Value for Receive and Transmit DMA
Defines the timeout value for receive and transmit DMA lockup detection, defined as a multiple of the prescaler value (PRESCALER). The MAC lockup time is defined in a separate configuration register (GMAC_LCKUP_TIME).
Bits 15:0 – PRESCALER[15:0] Prescaler Value for Timeout
Defines the prescaler value which is a multiple of the transmit clock.