8.2.169 GMAC Express MAC Transmit Status Register
| Name: | GMAC_EMAC_TSR |
| Offset: | 0x1014 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXDMALCK | TXMACLCK | HRESP | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCO | TXCOMP | TFC | TXGO | RLE | COL | UBR | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 10 – TXDMALCK Transmit DMA Lockup (Clear by Writing a 1)
Set when lockup has been detected on the DMA transmit path. Writing a one clears this bit.
Bit 9 – TXMACLCK Transmit MAC Lockup (Clear by Writing a 1)
Set when lockup has been detected on the MAC transmit path. Writing a one clears this bit.
Bit 8 – HRESP System Bus Response (Clear by Writing a 1)
Set when the DMA block sees a system bus error. Writing a one clears this bit.
Bit 7 – LCO Late Collision Occurred (Clear by Writing a 1)
Only set if the condition occurs in Gigabit mode, as retry is not attempted. Writing a one clears this bit.
Bit 5 – TXCOMP Transmit Complete (Clear by Writing a 1)
Set when a frame has been transmitted. Writing a one clears this bit.
Bit 4 – TFC Transmit Frame Corruption Due to System Bus Error (Clear by Writing a 1)
Transmit frame corruption due to system bus error. Set if an error occurs while midway through reading transmit frame from the system bus, including system bus errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted).
Also set in DMA packet buffer mode if a single frame is too large for the configured packet buffer memory size.
Writing a one clears this bit.
Bit 3 – TXGO Transmit Go (Read only)
When high, transmit is active. When using the DMA interface, this bit represents the TXGO variable as specified in the transmit buffer description.
Bit 2 – RLE Retry Limit Exceeded (Clear by Writing a 1)
Writing a one clears this bit.
Bit 1 – COL Collision Occurred (Clear by Writing a 1)
Set by the assertion of collision. Writing a one clears this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In Gigabit mode, this status is not set for a late collision.
Bit 0 – UBR Used Bit Read (Clear by Writing a 1)
Set when a transmit buffer descriptor is read with its used bit set. Writing a one clears this bit.