8.2.311 GMAC Express MAC Receive Queue Flush Register
This register defines the traffic policing mode of operation. Each mode can be set simultaneously with the exception of bits 2 and 3, which are exclusive. If bits 2 and 3 are both set then only bit 3 is treated as active
| Name: | GMAC_EMAC_RX_FLUSH_Q |
| Offset: | 0x1B00 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MAX_VAL[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MAX_VAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LIMIT_FRAME_SIZE | LIMIT_NUM_BYTES | DROP_ON_RESRC_ERR | DROP_ALL | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:16 – MAX_VAL[15:0] Maximum Value for the Received Frame Size or Number of 128-Byte Chunk
Defines the maximum value for the received frame size when the bit LIMIT_FRAME_SIZE=1 or the number of 128 byte chunks of data received for this queue and already stored in the memory of the queue awaiting DMA memory writes when LIMIT_NUM_BYTES=1 and LIMIT_FRAME_SIZE=0.
Bit 3 – LIMIT_FRAME_SIZE Maximum Frame-length Received
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | No effect. |
| 1 | ENABLED | When set, MAX_VAL indicates the maximum frame-length in bytes that may be received. Frames exceeding this length will be dropped. This traffic policing function is relevant to the 802.1Qci standard which specifies stream filtering based on a maximum service data unit (SDU) size. |
Bit 2 – LIMIT_NUM_BYTES Limitation of the Number of 128-Byte Chunk of Data Stored in the Memory of this Queue
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | No effect. |
| 1 | ENABLED | Limits the number of 128 byte chunks of data received for this queue and already stored in the memory of the queue awaiting DMA memory writes to the value defined in the field MAX_VAL. |
Bit 1 – DROP_ON_RESRC_ERR Drop on Resource Error
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | No effect. |
| 1 | ENABLED | If a free DMA descriptor for this queue cannot be obtained (also referred to as lack of descriptor resource and occurs when the software either cannot free up descriptors quickly enough to meet the receive traffic rate or has deliberately decided not to free any descriptors), all new frames received on this queue will be automatically discarded. |
Bit 0 – DROP_ALL Drop All Frames
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | No effect. |
| 1 | ENABLED | Drops all frames of this queue. |