8.2.145 GMAC ENST Control Register
| Name: | GMAC_ENST_CR |
| Offset: | 0x880 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN_Q5 | EN_Q4 | EN_Q3 | EN_Q2 | EN_Q1 | EN_Q0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5 – EN_Qx Enhanced Scheduled Traffic Enable for Queue x
| Value | Description |
|---|---|
| 0 | Disables the enhanced scheduled traffic for queue x. |
| 1 | Enables the enhanced scheduled traffic for queue x. EMAC has only 1 queue and ENST is enabled by writing EN_Q0. |