The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
Name:
GMAC_MMSL_IDR
Offset:
0xF20
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
SMD_ERR
FR_COUNT_ERR
SMDC_ERR
SMDS_ERR
RCV_V_ERR
RCV_R_ERR
Access
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit 5 – SMD_ERR Illegal SMD Received
Bit 4 – FR_COUNT_ERR Illegal SMD Received
Bit 3 – SMDC_ERR SMD-C Received When Waiting an SMD-S
Bit 2 – SMDS_ERR SMD-S Received When Waiting an SMD-C
Bit 1 – RCV_V_ERR Incorrect Verification Mpacket Received
Bit 0 – RCV_R_ERR Incorrect Response Mpacket Received
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
