8.2.156 GMAC MMSL Status Register
This register contains the status bits for the 802.3br MAC Merge Sublayer (MMSL).
| Name: | GMAC_MMSL_SR |
| Offset: | 0xF04 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SMD_ERR | FRER_COUNT_ERR | SMDC_ERR | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SMDS_ERR | RCV_V_ERR | RCV_R_ERR | VERIFY_STATUS[2:0] | RESPOND_STATUS | PRE_ACTIVE | ||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 10 – SMD_ERR Illegal Start Mpacket Delimiter Received (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | An illegal SMD (different from Express, Verify, Response, Start Preemptible or Continuation Preemptible SMD) has been received since the last read of GMAC_MMSL_SR. |
Bit 9 – FRER_COUNT_ERR Frame Counter Error (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | A frame counter error occurred since the last read of GMAC_MMSL_SR. A frame counter error occurs when the SMD-C received indicates a different frame count than expected (i.e. the fragment belongs to another frame and not to the Start packet already received before this) or when a fragment error occurred, which means the field following the SMD-C received was encoding a different fragment count than it was supposed to be. |
Bit 8 – SMDC_ERR SMD-C Received When Waiting an SMD-S (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | An SMD-C has been received when an SMD-S was expected, since the last read of GMAC_MMSL_SR. |
Bit 7 – SMDS_ERR SMD-S Received When Waiting an SMD-C (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | An SMD-S has been received when an SMD-C was expected, since the last read of GMAC_MMSL_SR. |
Bit 6 – RCV_V_ERR Incorrect Verification Mpacket Received (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | An incorrect verification mPacket has been received since the last read of GMAC_MMSL_SR. |
Bit 5 – RCV_R_ERR Incorrect Response Mpacket Received (Clear on read)
| Value | Description |
|---|---|
| 0 | No error since the last read of GMAC_MMSL_SR. |
| 1 | An incorrect response mPacket has been received since the last read of GMAC_MMSL_SR. |
Bits 4:2 – VERIFY_STATUS[2:0] Verification Status
| Value | Name | Description |
|---|---|---|
| 0 | INIT_VERIFICATION | Initialization |
| 1 | VERIFICATION_IDLE | Idle |
| 2 | SEND_VERIFY | Sending a verify command |
| 3 | WAIT_FOR_RESPONSE | Waiting for a response |
| 4 | VERIFIED | Verified |
| 5 | VERIFY_FAIL | Failure during the verify operation |
Bit 1 – RESPOND_STATUS Response Status
| Value | Name | Description |
|---|---|---|
| 0 | R_IDLE | Idle |
| 1 | SEND_RESPOND | Sending |
Bit 0 – PRE_ACTIVE Preemption Status
| Value | Description |
|---|---|
| 0 | Preemption is inactive. |
| 1 | Preemption is active when the verification process is completed or when GMAC_MMSL_CR.VERIFY_DISABLE=1 and GMAC_MMSL_CR.PRE_ACTIVE=1. |