8.2.24 GMAC Transmit DMA Lockup Control Register
| Name: | GMAC_TXDMA_LCKUP_CR |
| Offset: | 0x070 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCKUP_EN_Q5 | LCKUP_EN_Q4 | LCKUP_EN_Q3 | LCKUP_EN_Q2 | LCKUP_EN_Q1 | LCKUP_EN_Q0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5 – LCKUP_EN_Qx Transmit DMA Lockup Detector Enable for Queue x
| Value | Description |
|---|---|
| 0 | Disables the transmit DMA lockup timer for queue x. The number of outstanding packets is still counted but the actual timer does not run. |
| 1 | Enables the transmit DMA lockup timer for queue x. |