3.4.3.4.1.2 RXBC2 – RX Buffer Configuration Register 2
| Name: | RXB2 |
| Offset: | 0x130 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved[4:0] | RXBCLR | RXBF | RXBPB | ||||||
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:3 – Reserved[4:0] Reserved Bit
0’ when read.Bit 2 – RXBCLR RX Buffer Clear
1’ is written to this bit, the RX buffer aborts both channels with
an internal disable immediately and restarts the receive operation (soft reset). The
actual content of the shift register is not written to the DFIFO. The RXBCLR bit
returns the internal “clear” state of the RX buffer when read. If RXBCLR and RXBF
are written at the same time, RXBCLR is executed.Bit 1 – RXBF RX Buffer Finish
1’ is written to this bit, the RX buffer stops receiving
immediately and sends the received bits, which are available in the shift register
correctly aligned, to the DFIFO. Reception can be restarted by writing the RXBC bit
or by disabling and enabling the buffer in the corresponding power reduction
register. This bit returns the internal “finish” state when
read.Bit 0 – RXBPB RX Buffer Path B Select Signal
1 = Path B is selected as output to the DFIFO
0 = Path A is selected as output to the DFIFO