Description
This Tcl command defines a module for your project.
use_source_file \
-file {full pathname} \
-module value
Arguments
| Parameter | Type | Description |
|---|
| file | string | Specifies the Verilog or VHDL file. Value is the name of the file you wish use (including the full pathname). This is mandatory. |
| module | string | Specifies the module in which you want to use the file. This is mandatory. |
Error Codes
| Error Code | Description |
|---|
| None | Required parameter 'file' is missing. |
| None | Required parameter 'module' is missing. |
| None | 'file1.vhd' does not define module 'top'. |
| None | '/prj/hdl/file1.v' is not in the project. |
Supported Families
| Supported Families |
| PolarFire® |
| RTG4™ |
| SmartFusion® 2 |
| IGLOO® 2 |
Example
Specify file1.vhd in the ./project/hdl directory, in the module named top.
use_source_file -file "./project/hdl/file1.vhd" -module "top"
