21.3.62 new_project

Description

This Tcl command creates a new project in Libero SoC. If you do not specify a location, Libero SoC saves the new project in your current working directory.

new_project -name project_name \
-location project_location \
-family family_name \
-project_description "brief text description of project" \
-die device_die \
-package package_name \
-hdl HDL_type \
-speed speed_grade \
-die_voltage value \
-part_range value \
-block_mode {1 | 0} \
-ondemand_build_dh {1 | 0} \
-adv_options value \
-use_relative_path {1 | 0} \
-linked_files_root_dir_env root_dir_env \
-standalone_peripheral_initialization {1 | 0} \
-instantiate_in_smartdesign {1 | 0} \
-use_enhanced_constraint_flow {1 | 0}

Arguments

The following are advanced options for temperature and voltage settings.

The following are options for Analysis Operating Conditions so that Timing and Power analysis can be performed at different operating conditions.

Error Codes

Supported Families

Example

1. Creates a new project in the ./designs/mydesign directory, with the HDL type Verilog for the SmartFusion 2 family.

   new_project -location {./designs/mydesign} \
   -name {mydesign} \
   -use_enhanced_constraint_flow 1 \
   -use_relative_path 1 -linked_files_root_dir_env {MSCC_ROOT_1} \
   -standalone_peripheral_initialization 1 -hdl {VERILOG} -family {SmartFusion 2} \
   -die {M2S150TS} -package {FCS536} -speed {-1} -die_voltage {1.2} \
   -part_range {COM} -adv_options {DSW_VCCA_VOLTAGE_RAMP_RATE:100_MS} \
   -adv_options {IO_DEFT_STD:LVCMOS 2.5V} \
   -adv_options {PLL_SUPPLY:PLL_SUPPLY_25} \
   -adv_options {RESTRICTPROBEPINS:1} \
   -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
   -adv_options {TEMPR:IND} -adv_options {VCCI_1.2_VOLTR:IND} \
   -adv_options {VCCI_1.5_VOLTR:IND} -adv_options {VCCI_1.8_VOLTR:IND} \
   -adv_options {VCCI_2.5_VOLTR:IND} -adv_options {VCCI_3.3_VOLTR:IND} \
   -adv_options {VOLTR:IND}

2. Creates a new project in the D:/2Work/my_pf_proj directory, with the HDL type Verilog for PolarFire. Sets up a new design and runs Libero tools.

   new_project -location {D:/2Work/my_pf_proj} -name {my_pf_proj} \
   -project_description {} - block_mode 0 -standalone_peripheral_initialization 0 \
   -use_enhanced_constraint_flow 1 -use_relative_path 1 \ 
   -linked_files_root_dir_env {MSCC_ROOT_1} -hdl {VERILOG} -family {PolarFire} \
   -die {MPF300TS_ES} -package {FCG1152} -speed {-1} - die_voltage {1.0} \
   -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} \
   -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:1} \
   -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} \
   -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} \
   -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT} 
   #Import HDL source file
   import_files -convert_EDN_to_HDL 0 -hdl_source {C:/test/prep1.v}
   
   #Import HDL stimulus file
   import_files -convert_EDN_to_HDL 0 -stimulus {C:/test/prep1tb.v}
   #set the top level design name
   set_root -module {prep1::work}
   
   #Associate SDC constraint file to Place and Route tool
   organize_tool_files -tool {PLACEROUTE} -file {D:/2Work/my_pf_proj/constraint/user.sdc} \
   -module {prep1::work} -input_type {constraint}
   
   #Associate SDC constraint file to Verify Timing tool
   organize_tool_files -tool {VERIFYTIMING} -file {D:/2Work/my_pf_proj/constraint/user.sdc} \ 
   -module {prep1::work} -input_type {constraint}
   #Run synthesize
   run_tool -name {SYNTHESIZE}
   #Configure Place and Route tool
   configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:false} \
   -params {INCRPLACEANDROUTE:false} -params {MULTI_PASS_CRITERIA:VIOLATIONS} \
   -params {MULTI_PASS_LAYOUT:false} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} \ 
   -params {RANDOM_SEED:0} -params {REPAIR_MIN_DELAY:false} -params {SLACK_CRITERIA:WORST_SLACK} \
   -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:1} -params {STOP_ON_FIRST_PASS:false} \
   -params {TDPR:true}