3.3.19.2.1 Instruction Stall Cycles And Interrupts

When an interrupt event coincides with two adjacent instructions that causes an instruction stall, one of two possible outcomes can occur.

If the interrupt coincides with the first instruction, the first instruction is allowed to complete while the second instruction is executed after the ISR completes. In this case, the stall cycle is eliminated from the second instruction because the exception process provides time for the first instruction to complete the write phase.

If the interrupt coincides with the second instruction, the second instruction and the appended stall cycle are allowed to execute before the ISR. In this case, the stall cycle associated with the second instruction executes normally. However, the stall cycle is effectively absorbed into the exception process timing. The exception process proceeds as if an ordinary two-cycle instruction was interrupted.