20.18.12 PMC CPU Clock Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Only one of CSS and PRES fields can be modified at a time. When one of these parameters is modified, no other modification can be performed on these fields as long as the MCKRDY/CPMCKRDY status flags are low.
| Name: | PMC_CPU_CKR |
| Offset: | 0x002C |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RATIO_MCK0DIV2 | RATIO_MCK1DIV | RATIO_MCK0DIV | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CPPRES[3:0] | CPCSS[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRES[2:0] | CSS[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 1 | ||||
Bit 26 – RATIO_MCK0DIV2 MCK0 Clock Frequency Division for MCK0DIV2 Clock
| Value | Description |
|---|---|
| 0 | MCK0DIV2 frequency is the same as MCK0. |
| 1 | MCK0DIV2 frequency is MCK0 frequency divided by 2. |
Bit 25 – RATIO_MCK1DIV MCK1 Clock Frequency Division for MCK1DIV Clock
| Value | Description |
|---|---|
| 0 | MCK1DIV frequency is the same as MCK1. |
| 1 | MCK1DIV frequency is MCK1 frequency divided by 2. |
Bit 24 – RATIO_MCK0DIV MCK0 Clock Frequency Division for MCK0DIV Clock
| Value | Description |
|---|---|
| 0 | MCK0DIV frequency is the same as MCK0. |
| 1 | MCK0DIV frequency is MCK0 frequency divided by 2. |
Bits 23:20 – CPPRES[3:0] Coprocessor Clock Prescaler
Selected clock is divided by (CPPRES + 1).
Bits 18:16 – CPCSS[2:0] Coprocessor MCK1 Source Selection
| Value | Name | Description |
|---|---|---|
| 0 | SLOW_CLK | MD_SLCK is selected |
| 1 | MAIN_CLK | MAINCK is selected |
| 2 | MCK0 | MCK0 is selected |
| 3 | PLLACK1 | PLLACK1 is selected |
| 4 | PLLBCK | PLLBCK is selected |
| 5 | PLLCCK | PLLCCK is selected |
Bits 6:4 – PRES[2:0] Processor (CPU_CLK0) and Main System Bus Clock (MCK0) Prescaler
| Value | Name | Description |
|---|---|---|
| 0 | CLK_1 | Selected clock |
| 1 | CLK_2 | Selected clock divided by 2 |
| 2 | CLK_4 | Selected clock divided by 4 |
| 3 | CLK_8 | Selected clock divided by 8 |
| 4 | CLK_16 | Selected clock divided by 16 |
| 5 | CLK_32 | Selected clock divided by 32 |
| 6 | CLK_64 | Selected clock divided by 64 |
| 7 | CLK_3 | Selected clock divided by 3 |
Bits 1:0 – CSS[1:0] Processor (CPU_CLK0) and Main System Bus Clock (MCK0) Source Selection
| Value | Name | Description |
|---|---|---|
| 0 | SLOW_CLK | MD_SLCK is selected |
| 1 | MAIN_CLK | MAINCK is selected |
| 2 | PLLACK1 | PLLACK1 is selected |
| 3 | PLLBCK | PLLBCK is selected |