20.18.16 PMC Status Register
| Name: | PMC_SR |
| Offset: | 0x006C |
| Reset: | 0x00030008 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PLL_INT | GCLKRDY | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MCKMON | XT32KERR | FOS | CFDS | CFDEV | MOSCRCS | MOSCSELS | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCKRDY3 | PCKRDY2 | PCKRDY1 | PCKRDY0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSCSELS | CPMCKRDY | MCKRDY | MOSCXTS | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 1 | 0 |
Bit 25 – PLL_INT PLL Interrupt Status
| Value | Description |
|---|---|
| 0 | No PLL interrupt has occurred |
| 1 | A PLL interrupt has occurred. PLL interrupt is defined by the configuration of the PMC_PIMR register. |
Bit 24 – GCLKRDY GCLK Ready
| Value | Description |
|---|---|
| 0 | A GCLK is not ready to use (clock switching in progress). |
| 1 | All GCLK are switched on their selected source clock and ready to use. |
Bit 23 – MCKMON Main System Bus Clock (MCK0) Monitor Error
This status is cleared on read.
| Value | Description |
|---|---|
| 0 | The MCK0 clock is correct or the clock monitor is disabled. |
| 1 | The MCK0 clock is incorrect or has been incorrect for an elapsed period of time since the clock monitor has been enabled. |
Bit 21 – XT32KERR Slow Crystal Oscillator Error
| Value | Description |
|---|---|
| 0 | The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz ±1%) or the monitoring is disabled. |
| 1 | The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed period of time since the monitoring has been enabled. |
Bit 20 – FOS Clock Failure Detector Fault Output Status
| Value | Description |
|---|---|
| 0 | The fault output of the clock failure detector is inactive. |
| 1 | The fault output of the clock failure detector is active. This status is cleared by writing a ‘1’ to FOCLR in PMC_FOCR. |
Bit 19 – CFDS Clock Failure Detector Status
| Value | Description |
|---|---|
| 0 | A clock failure of the Main crystal oscillator clock is not detected. |
| 1 | A clock failure of the Main crystal oscillator clock is detected. |
Bit 18 – CFDEV Clock Failure Detector Event
| Value | Description |
|---|---|
| 0 | No clock failure detection of the Main crystal oscillator clock has occurred since the last read of PMC_SR. |
| 1 | At least one clock failure detection of the Main crystal oscillator clock has occurred since the last read of PMC_SR. |
Bit 17 – MOSCRCS Main RC Oscillator Status
| Value | Description |
|---|---|
| 0 | Main RC oscillator is not stabilized. |
| 1 | Main RC oscillator is stabilized. |
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status
| Value | Description |
|---|---|
| 0 | Selection is in progress. |
| 1 | Selection is done. |
Bits 8, 9, 10, 11 – PCKRDYx Programmable Clock Ready Status
| Value | Description |
|---|---|
| 0 | Programmable Clock x is not ready. |
| 1 | Programmable Clock x is ready. |
Bit 7 – OSCSELS Monitoring Domain Slow Clock Source Oscillator Selection
| Value | Description |
|---|---|
| 0 | Slow RC oscillator is selected. |
| 1 | 32.768 kHz crystal oscillator is selected. |
Bit 4 – CPMCKRDY Coprocessor Clock (CPU_CLK1) and Main System Bus Clock (MCK1) Ready Status
| Value | Description |
|---|---|
| 0 | Not ready. |
| 1 | Ready. |
Bit 3 – MCKRDY Processor Clock (CPU_CLK0) and Main System Bus Clock (MCK0) Ready Status
| Value | Description |
|---|---|
| 0 | Not ready. |
| 1 | Ready. |
Bit 0 – MOSCXTS Main Crystal Oscillator Status
| Value | Description |
|---|---|
| 0 | Main crystal oscillator is not stabilized. |
| 1 | Main crystal oscillator is stabilized. |