20.18.39 PMC PLL Interrupt Mask Register
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | PMC_PLL_IMR |
| Offset: | 0x00EC |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| UNLOCK2 | UNLOCK1 | UNLOCK0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LOCK2 | LOCK1 | LOCK0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |