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20.18.30 PMC Peripheral Clock Status Register 1 “PIDx” refers to
identifiers as defined in the section “Peripheral Identifiers”.The
following configuration values are valid for all listed bit names of this
register:
0: The corresponding peripheral clock is
disabled.
1: The corresponding peripheral clock is
enabled.
Name: PMC_CSR1 Offset: 0x00A8 Reset: 0x00000000 Property: Read-only
Bit 31 30 29 28 27 26 25 24 PID59 PID57 Access R R Reset 0 0
Bit 23 22 21 20 19 18 17 16 PID55 PID53 PID51 PID49 Access R R R R Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 27 – PID59 Peripheral Clock x Status
Bit 25 – PID57 Peripheral Clock x Status
Bit 23 – PID55 Peripheral Clock x
Status
Bit 21 – PID53 Peripheral Clock x
Status
Bit 19 – PID51 Peripheral Clock x Status
Bit 17 – PID49 Peripheral Clock x
Status
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PID32, PID33, PID34, PID35, PID36, PID37, PID38,
PID39 Peripheral Clock x Status
On this page
Bit 27 – PID59 Peripheral Clock x Status Bit 25 – PID57 Peripheral Clock x Status Bit 23 – PID55 Peripheral Clock x
Status Bit 21 – PID53 Peripheral Clock x
Status Bit 19 – PID51 Peripheral Clock x Status Bit 17 – PID49 Peripheral Clock x
Status Bits 0, 1, 2, 3, 4, 5, 6, 7 – PID32, PID33, PID34, PID35, PID36, PID37, PID38,
PID39 Peripheral Clock x Status
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
