20.18.28 PMC MCK0 Monitor Limits Register
| Name: | PMC_MCKLIM |
| Offset: | 0x00A0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MCK_HIGH_RES[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MCK_LOW_RES[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MCK_HIGH_IT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MCK_LOW_IT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – MCK_HIGH_RES[7:0] MCK0 Monitoring High Reset Limit
Beyond this limit, the MCK0 frequency monitor generates a reset.
Bits 23:16 – MCK_LOW_RES[7:0] MCK0 Monitoring Low RESET Limit
Below this limit, the MCK0 frequency monitor generates a reset.
Bits 15:8 – MCK_HIGH_IT[7:0] MCK0 Monitoring High IT Limit
Beyond this limit, the MCK0 frequency monitor generates an interrupt.
Bits 7:0 – MCK_LOW_IT[7:0] MCK0 Monitoring Low IT Limit
Below this limit, the MCK0 frequency monitor generates an interrupt.