20.18.4 PMC PLL Control Register 0

All fields defined here are applied to the PLL defined by the last ID field written in PMC_PLL_UPDT.

Name: PMC_PLL_CTRL0
Offset: 0x000C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 ENLOCKENPLLO1ENPLLO0ENPLLPLLMS    
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
     DIVPMC1[7:4] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
 DIVPMC1[3:0]     
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 DIVPMC0[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – ENLOCK Enable PLL Lock

ValueDescription
0

The lock signal sent by the PLL is ignored. The PLL is considered as locked once the start-up time defined by PMC_PLL_UPDT.STUPTIM has elapsed.
1

The PLL is considered as locked once the start-up time defined by PMC_PLL_UPDT.STUPTIM has elapsed and the lock signal sent by the PLL has risen.

Bit 30 – ENPLLO1 Enable PLL Clock Output 1 (PLLA only)

ValueDescription
0

The output clock 1 generated by the PLL is disabled (DIVPMC1 must be set to 0 to get the PLL output clock 1 disabled).
1

The output clock 1 generated by the PLL is active.

Bit 29 – ENPLLO0 Enable PLL Clock Output 0

ValueDescription
0

The output clock 0 generated by the PLL is disabled (DIVPMC0 must be set to 0 to get the PLL output clock 0 disabled).
1

The output clock 0 generated by the PLL is active.

Bit 28 – ENPLL Enable PLL

ValueDescription
0

The PLL is off.
1

The PLL is on.

Bit 27 – PLLMS PLL Multiplexer Select

ValueDescription
0

PLL Multiplexer select input is set to ‘0’.
1

PLL Multiplexer select input is set to ‘1’.

Bits 19:12 – DIVPMC1[7:0] Divider for PMC Output 1 (PLLA only)

Specifies the division ratio applied to the internal PLL clock to generate PLLACK1.

Bits 7:0 – DIVPMC0[7:0] Divider for PMC Output 0

Specifies the division ratio applied to the internal PLL clock to generate PLLACK0, PLLBCK and PLLCCK.