20.18.9 PMC PLL Update Register
| Name: | PMC_PLL_UPDT |
| Offset: | 0x0020 |
| Reset: | 0x00030000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| STUPTIM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UPDATE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 23:16 – STUPTIM[7:0] Start-up Time
The start-up time is defined as a number of MD_SLCK cycles and is the same for all PLLs.
| Value | Description |
|---|---|
| 0 | Only the lock of the PLL is considered to know the lock status of the PLL. If the lock of the PLL is not enabled, the lock never rises. |
| Other values | If PMC_PLL_CTRL0.ENLOCK is low, specifies the start-up time of the PLL. If PMC_PLL_CTRL0.ENLOCK is high, specifies how long the LOCK signal of the PLL is masked before being read. |
Bit 8 – UPDATE PLL Setting Update (write-only)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The PLL configuration written in PMC_PLL_CTRL0 and PMC_PLL_CTRL1 are applied to the PLL defined by the last ID written in the PMC_PLL_UPDT register. |
Bits 3:0 – ID[3:0] PLL ID
When writing a PLL control register (PMC_PLL_CTRLx), this ID specifies which PLL is impacted by written fields.
When reading a PLL control register (PMC_PLL_CTRLx), this ID specifies which PLL fields are read.