20.18.13 PMC Programmable Clock Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | PMC_PCKx |
| Offset: | 0x44 + x*0x04 [x=0..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRES[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSS[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 15:8 – PRES[7:0] Programmable Clock Prescaler
| Value | Description |
|---|---|
| 0–255 | Selected clock is divided by PRES+1. |
Bits 4:0 – CSS[4:0] Programmable Clock Source Selection
Values not listed are considered ‘reserved’.
| Value | Name | Description |
|---|---|---|
| 0 | MD_SLOW_CLK | MD_SLCK is selected |
| 1 | TD_SLOW_CLOCK | TD_SLCK is selected |
| 2 | MAINCK | MAINCK is selected |
| 3 | MCK0 | MCK0 is selected |
| 4 | PLLACK1 | PLLACK1 is selected. |
| 5 | PLLBCK | PLLBCK is selected. |
| 6 | PLLCCK | PLLCCK is selected. |
| 7 | PLLCSRC | PLLCSRC is selected. |