20.18.15 PMC Interrupt Disable Register

This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name:	PMC_IDR
Offset:	0x0068
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	MCKMON		XT32KERR			CFDEV	MOSCRCS	MOSCSELS
Access	W		W			W	W	W
Reset	–		–			–	–	–


Bit	15	14	13	12	11	10	9	8
					PCKRDY3	PCKRDY2	PCKRDY1	PCKRDY0
Access					W	W	W	W
Reset					–	–	–	–


Bit	7	6	5	4	3	2	1	0
				CPMCKRDY	MCKRDY			MOSCXTS
Access				W	W			W
Reset				–	–			–

Bit 23 – MCKMON Main System Bus Clock (MCK0) Monitor Interrupt Disable

Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable

Bit 18 – CFDEV Clock Failure Detector Event Interrupt Disable

Bit 17 – MOSCRCS Main RC Status Interrupt Disable

Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Disable

Bits 8, 9, 10, 11 – PCKRDYx Programmable Clock Ready x Interrupt Disable

Bit 4 – CPMCKRDY Coprocessor Clock (CPU_CLK1) and Main System Bus Clock (MCK1) Ready Interrupt Disable

Bit 3 – MCKRDY Processor Clock (CPU_CLK0) and Main System Bus Clock (MCK0) Ready Interrupt Disable

Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Disable

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