20.18.32 PMC Peripheral Clock Status Register 3

“PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.

The following configuration values are valid for all listed bit names of this register:

0: The corresponding peripheral clock is disabled.

1: The corresponding peripheral clock is enabled.

Name: PMC_CSR3
Offset: 0x00B0
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        PID96 
Access R 
Reset 0 

Bit 0 – PID96 Peripheral Clock x Status