9.3.8.3 MISC_REG Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| 1 | TX_EDMA | 0 | 0: DMA_REQ signal for all IN endpoints is
deasserted when MAXP (TX_MAX_P_REG) bytes are written to an endpoint. This is a
late mode. 1: DMA_REQ signal for all IN endpoints is deasserted when MAXP-8 (TX_MAX_P_REG-8) bytes are written to an endpoint. This is an early mode. |
| 0 | RX_EDMA | 0 | 0: DMA_REQ signal for all OUT endpoints is
deasserted when MAXP (TX_MAX_P_REG) bytes are read to an endpoint. This is a
late mode. 1: DMA_REQ signal for all OUT endpoints is deasserted when MAXP-8 (TX_MAX_P_REG-8) bytes are read to an endpoint. This is an early mode. |