10.1.14 Decrementer
A Decrementer is a logic block that reduces the input value by one, producing the decremented result.
Supported Families
The following is a list of the supported families:
- IGLOO®
- ProASIC®3
- SmartFusion®
- Fusion®
- ProASIC PLUS®
- ProASIC®
- Axcelerator®
- RTAX-S
- SX-A
- eX
Related Topics
Key Features
A Decoder has the following key features:
- Parameterized word length
- Optional Carry-out signals
- One very fast gate-level implementation, FC High Speed and FC Ripple available
- Behavioral simulation RTL in VHDL and Verilog