10.1.2 Adder

An adder is a combinational logic block that performs arithmetic addition of two input operands and produces a sum (and optionally a carry output).

The following figure displays an adder.

Figure 10-2. Adder
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Supported Families

The following is a list of the supported families:
  • IGLOO®
  • ProASIC® 3
  • SmartFusion®
  • Fusion®
  • ProASICPLUS®
  • ProASIC®
  • Axcelerator®
  • SX-S
  • SX-A
  • eX

Related Topics

Key Features

An adder has the following key features:
  • Parameterized word length
  • Optional carry-in and carry-out signals
  • Multiple gate-level implementations (speed/area tradeoffs)
  • Behavioral simulation RTL in VHDL and Verilog

For the Sklansky adder, you can clear the Automatic Max. Fanout check box and specify a value for max fanout. This makes the software perform logic replication on high-fanout nets, so that the maximum fanout for all the nets in the design is not more than the value specified. If it is set to automatic, the software automatically makes the decision for logic replication based on the size of the design.