10.1.33 Shift Register
A Shift Register is a configurable logic block that stores data and shifts it sequentially through register stages under clock control.
The following figure displays the view of the Shift Register element.
Supported Families
The following is a list of the supported families:
- IGLOO®
- ProASIC®3
- SmartFusion®
- Fusion®
- ProASIC®PLUS
- ProASIC®
- Axcelerator®
- RTAX-S
- eX
- SX-A
Related Topics
Key Features
- Parameterized word length
- Asynchronous clear
- Synchronous parallel load
- Behavioral simulation RTL in VHDL and Verilog