Jump to main content
Libero IDE v9.x
Libero IDE v9.x
  1. Home
  2. 10 SmartGen Cores Reference
  3. 10.1 Basic Blocks
  4. 10.1.18 Input Buffers
Previous | Next
  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
    • 10.1 Basic Blocks
      • 10.1.1 Accumulator
      • 10.1.2 Adder
      • 10.1.3 Array Adder
      • 10.1.4 Adder/Subtractor
      • 10.1.5 Constant Decoder
      • 10.1.6 Magnitude/Equality Comparator
      • 10.1.7 Binary to Gray/Gray to Binary Converters
      • 10.1.8 Gray Counter
      • 10.1.9 Linear Binary Counters
      • 10.1.10 Linear Binary Counters IGLOO®, ProASIC® 3, SmartFusion® and Fusion Summary
      • 10.1.11 CRC Minicore
      • 10.1.12 Dual Data Rate (DDR) Register
      • 10.1.13 Decoder
      • 10.1.14 Decrementer
      • 10.1.15 FIR Filter
      • 10.1.16 Bi-Directional Buffers
      • 10.1.17 Global Buffers
      • 10.1.18 Input Buffers
        • 10.1.18.1 Input Buffers I/O Description
        • 10.1.18.2 Input Buffers Parameter Description
        • 10.1.18.3 Input Buffers Implementation Rules
      • 10.1.19 Output Buffers
      • 10.1.20 PECL Global Buffers
      • 10.1.21 Tri-State Buffers
      • 10.1.22 Incrementer
      • 10.1.23 Incrementer/Decrementer
      • 10.1.24 Logic - AND
      • 10.1.25 Logic - OR
      • 10.1.26 Logic - XOR
      • 10.1.27 Multiplexor
      • 10.1.28 Multiplier
      • 10.1.29 Constant Multiplier
      • 10.1.30 Register File for eX and SX-A
      • 10.1.31 Register File for ProASICPLUS®
      • 10.1.32 Barrel Shifter
      • 10.1.33 Shift Register
      • 10.1.34 Storage Register
      • 10.1.35 Storage Latch
      • 10.1.36 Subtractor
    • 10.2 Clock and Management
    • 10.3 Fusion Peripherals
    • 10.4 Memory and Controllers
    • 10.5 Power Management
    • 10.6 Revision History
    • 10 Microchip FPGA Support
    • 10 Microchip Information
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

10.1.18 Input Buffers

Input buffers with a specified data width.

Supported Families

The following is a list of the supported families:
  • IGLOO®
  • ProASIC®3
  • SmartFusion®
  • Fusion®
  • ProASIC®PLUS
  • ProASIC®
  • Axcelerator®
  • RTAX-S
  • eX
  • SX-A

Related Topics

  • Input Buffers I/O Description
  • Input Buffers Parameter Description
  • Input Buffers Implementation Rules

Key Features

  • Parameterized for data width
  • Choice of data buffers (Regular, Special, Pull-Up, Pull-Down)
On this page
  • Supported Families
  • Related Topics
  • Key Features

Rev: A

About

Company
Careers
Contact Us
Media Center
Investor Relations
Corporate Responsibility

Support

Microchip Forums
AVR Freaks
Design Help
Technical Support
Export Control Data
PCNs

Quick Links

microchipDIRECT.com
Microchip University
myMicrochip
Blogs
Reference Designs
Parametric Search
Microchip Logo

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Facebook
Microchip LinkedIn
Microchip Twitter
Microchip Instagram
Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use
Privacy Notice
Legal
Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon