10.1.6 Magnitude/Equality Comparator
A Magnitude/Equality Comparator is a combinational logic block that compares two input values and indicates whether one is greater than, less than or equal to the other.
Supported Families
The following is a list of the supported families:
- IGLOO®
- ProASIC® 3
- SmartFusion®
- Fusion®
- ProASICPLUS®
- ProASIC®
- Axcelerator®
- RTAX-S
- SX-A
- eX
Related Topics
Key Features
- Parameterized word length
- Unsigned and signed (Two’s-Complement) data comparison
- One very fast gate level implementation
- Behavioral simulation RTL in VHDL and Verilog