10.1.31 Register File for ProASICPLUS®
The register file for ProASICPLUS provides distributed memory implemented using logic tiles and can be configured as a two-port asynchronous register file.
The following figure displays the view of the Register File for ProASICPLUS core.
Supported Families
The following is a list of the supported families:
- ProASIC®PLUS
Description
Distributed memory can be generated as a two-port asynchronous register file or as an asynchronous FIFO. Distributed memories are made up of the logic tiles of the device. These memory files are netlists consisting of logic tiles and do not use embedded memory cells.
Related Topics
Key Features
- Parameterized word length and depth
- Two-port asynchronous register file
- Rising-edge triggered or level-sensitive
- Supported netlist formats: VHDL and Verilog