10.1.3 Array Adder

An Array adder is a structured implementation of an adder that uses an array of interconnected full adders to perform binary addition, typically optimized for regular layout and predictable timing.

The following figure displays an Array adder.

Figure 10-5. Array adder
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Supported Families

The following is a list of the supported families:
  • IGLOO®
  • ProASIC® 3
  • SmartFusion®
  • Fusion®
  • ProASICPLUS®
  • ProASIC®
  • Axcelerator®
  • SX-S
  • SX-A
  • eX

Related Topics

Key Features

  • Parameterized word length and number of input buses
  • DADDA tree architecture with optional Final adder
  • Optional pipeline for implementation with Final adder
  • Behavioral simulation RTL in VHDL and Verilog

The Array-Adder implements a Sum-Function over an array of buses:

Sum = [Summation(Data(i))] where i = 0 to Size-1

In applications where designers have to add more than two operands at a time, “Carry-Save- Techniques” might be used to build the final sum. The software makes these techniques available through the Array-Adder core, which is using a DADDA tree algorithm. Usually, this algorithm is more compact and faster than using adder trees consisting of multiple two-operand adders, especially if the number of operands gets large and/or for large word width.

An example could be the FIR-filter architecture using a “distributed arithmetic” as described in the Application Note from September 1997 Designing FIR Filters with Microchip FPGAs. This architecture generates a large number of partial products, which need to be summed. Summing them in an Adder-Tree would both be slow and area-expensive. At the time of writing this document, synthesis tools did not infer Multiple-Operand-Adders. Therefore, making use of the Array-Adder in those types of applications might result in a significant gain in both speed and area.

The Array adder comes with or without Final adder. The version with Final adder allows the software to instantiate a pipeline stage between the Dadda-tree and the Final adder. The output bitwidth for Sum can be calculated using this formula:

OUTWIDTH = log2((m*exp2(n)-1)+1) <= n + log2(m)

The version without Final adder has two output ports, SumA and SumB, which added together provides the final result, which is:

SumA_Width <= SumB_Width <= OUTWIDTH

The differences are at most one bit. This variation of the Array-Adder is particularly useful for an application that would cascade the Array-Adder. In that case only the last stage would need a Final adder to build the result.