10.1.10 Linear Binary Counters IGLOO®, ProASIC® 3, SmartFusion® and Fusion Summary

If you are not using a IGLOO®, ProASIC® 3, SmartFusion® and Fusion device, see the Linear Binary Counter description for all other devices.

Features

  • Parameterized word length
  • Up, Down and Up/Down architectures
  • Asynchronous clear
  • Asynchronous preset
  • Synchronous counter load
  • Synchronous count enable
  • Terminal count flag
  • Multiple gate-level implementations (area/speed tradeoffs)
  • Behavioral simulation RTL in VHDL and Verilog

The binary counters are general-purpose UP, DOWN or UP/DOWN (direction) counters.

When used, the Tcnt (terminal count) signal is asserted when the count value equals 2width-1 for Up counters, or 0 for Down counters.

Note: Tcnt is not supported for Up/Down counters.

The counters are WIDTH bits wide and have 2width states from “000…0” to “111…1”. The counters are clocked on the rising (RISE) or falling (FALL) edge of the clock signal Clock (CLK_EDGE).

The Aclr signal (CLR_POLARITY), active low or high, provides an asynchronous clear of the counter to “000…0”. You may choose not to implement the clear function. If you do not use the Aclr signal, then you must use at least one of the Aset or Sload signals to set the initial counter contents to a known value.

The Aset signal (SET_POLARITY), active low or high, provides an asynchronous preset of the counter to “111…1”. You may choose not to implement the preset function. If you do not use the Aset signal, then you must use at least one of the Aclr or Sload signals to set the initial counter contents to a known value.

If used, the Aclr/Aset signals must be made global; otherwise, a 2-tile implementation of the flip-flops is used, doubling the number of SEQ (sequential) modules. An example of the pdc entry is:

–net Aclr

In the case of an Up/Down counter, the Updown signal controls whether the counter counts up (Updown = 1) or down (Updown = 0).

The counter could be loaded with Data. The Sload signal (LD_POLARITY), active high or low, provides a synchronous load operation with respect to the clock signal Clock. You can choose not to implement this function. If you do not use the Sload signal, then you must use either Aclr or Aset to set the initial counter contents to a known value.

The counter can have an Enable signal (EN_POLARITY), active low or high. You are not required to have an Enable signal. When Enable is not active, the counter is disabled and the internal state is unchanged.

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