10.1.30 Register File for eX and SX-A

The Register File is a configurable logic core that provides register storage implemented using ordinary logic for device families without dedicated RAM blocks.

The following figure displays the view of the Register File core.

Figure 10-35. Register File for eX and SX-A
Register File for eX and SX-A

Supported Families

The following is a list of the supported families:
  • eX
  • SX-A

Related Topics

Key Features

  • Parameterized word length and depth
  • Dual-port synchronous RAM architecture
  • Dual-port synchronous write, asynchronous read RAM architecture
  • Write and read enable
  • Behavioral simulation RTL in VHDL and Verilog

Description

The register file is a core unique to the SX, SX-A and eX families. This core synthesizes the equivalent of small RAM blocks using ordinary logic, thereby making memory cells available even though the silicon does not explicitly have hardware support for RAM.

In synchronous mode, the read and write operations are totally independent and can be performed simultaneously. The operation of the register is fully synchronous with respect to the clock signals WClock and RClock. Data of value Data are written to the WAddress of the register memory space on the rising (RISE) or falling (FALL) edge of the clock WClock (WCLK_EDGE). Data are read from the register memory space at RAddress into Q on the rising (RISE) or falling (FALL) edge of the clock RClock (RCLK_EDGE).

The behavior of the register is unknown if designers write and read at the same address and WClock and RClock are not the same. The output Q of the register depends on the time relationship between the write and the read clock.

In asynchronous mode, the operation of the register is only synchronous with respect to the clock signal WClock. Data of value Data are written to the WAddress of the register memory space on the rising (RISE) or falling (FALL) edge of the clock WClock (WCLK_EDGE). Data are read from the register memory space at RAddress into Q after some delay when RAddress has changed.

The WIDTH (word length) and DEPTH (number of words) have continuous values, but the choice of WIDTH limits the choice of DEPTH and vice versa.

The write enable (WE) and read enable (RE) signals are active-high request signals for writing and reading, respectively. You may not utilize them.