10.1.13 Decoder
A Decoder is a combinational logic block that translates encoded input signals into a one-hot or mutually exclusive set of output signals.
Supported Families
The following is a list of the supported families:
- IGLOO®
- ProASIC®3
- SmartFusion®
- Fusion®
- ProASIC PLUS®
- ProASIC®
- Axcelerator®
- RTAX-S
- SX-A
- eX
Related Topics
Key Features
A Decoder has the following key features:
- Parameterized output size
- Behavioral simulation RTL in VHDL and Verilog