10.1.15 FIR Filter

An FIR Filter is a digital signal processing block that implements a finite impulse response filter using a weighted sum of input samples.

Figure 10-21. FIR Filter
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Supported Families

The following is a list of the supported families:
  • IGLOO®
  • ProASIC®3
  • SmartFusion®
  • Fusion®
  • ProASIC PLUS®
  • ProASIC®
  • Axcelerator®
  • SX-A
  • eX

Related Topics

Key Features

An FIR Filter has the following key features:
  • Variable input data width: 2-bit to 16-bit input data
  • Variable output data width: 3-bit to 64-bit output data
  • Support for up to 64 taps
  • Support of symmetric coefficients
  • Optional I/O insertion
  • Optional registers for filter in- and output
  • Verilog RTL model for simulation
  • VHDL RTL model for synthesis (synthesized filter designs are usually slower, but more compact)

    FIR Filter Design Flow

The following diagram displays an overview of the design flow required for the FIR filter.

Figure 10-22. FIR Filter Design Flow
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