10.1.29 Constant Multiplier
A Constant Multiplier is a configurable logic block that performs the multiplication of a data input with a constant value.
The following figure displays the view of the Constant Multiplier element.
Supported Families
- IGLOO®
- ProASIC®3
- SmartFusion®
- Fusion®
- ProASIC®PLUS
- ProASIC®
- Axcelerator®
- SX-S
- SX-A
- eX
Related Topics
Key Features
- Parameterized word lengths and constant values
- Unsigned and signed (Two’s-Complement) data representation
- Booth/Wallace architecture
- Behavioral simulation RTL (for non-pipelined multiplier only) in VHDL and Verilog
The Constant Multiplier core output wordlength is always double the input word length. Depending on the value of the constant, some of the most significant bits might be sign-extension bits. You may be able to reduce hardware by calculating the actual number of bits needed and cutting all sign-extension bits. For example:
width = 4, Constant = 1100, representation=signed
The worst case data for this example would be 1000 (-8) and therefore the worst case output data would be 010 0000 (-8 * -4 = 32). So with that we know that Mult<8> is just a sign-extension bit (Mult<8> = Mult<7>).
Keep in mind that some constant multiplications might be generated even more effectively, for example, constants to the power of 2 are just shift-operations, or constants like 3,5,7,9,10, and more can be generated using shift operations and a simple addition/subtraction (2 + 1, 4 + 1, 8 - 1, 8 + 1, 8 + 2, and more). For these constants, the implementation of the Constant Multiplier might not be as efficient as using shift operations and/or Adders/Subtractors.
Usually synthesis infers regular Multipliers even for constant values. Therefore the use of the Constant Multiplier core in a design, which performs one or more multiplications with constant values, is expected to be very beneficial.