5.34.111.1 Examples

Syntax for the get_defvar command followed by a sample command:

get_defvar variable

get_defvar “DESIGN”

Syntax for the backannotate command followed by a sample command:

backannotate -name file_name -format format_type -language language -dir directory_name [-netlist] [-pin]

backannotate -dir \

{..\design} -name "fanouttest_ba.sdf" -format "SDF" -language "VERILOG" \

-netlist

timer_get_clock_actuals

Displays the actual clock frequency in the Log window, when the timing analysis tool is initiated.

timer_get_clock_actuals -clock clock_name

Deletes a probe on nets in a probed ADB file.

delete_probe –net <net_name>

Displays the actual clock frequency in the Log window, when the timing analysis tool is initiated.

timer_get_clock_actuals -clock clock_name

Restores constraints previously committed in Timer.

timer_restore

Creates a new clock or set domain.

smartpower_create_domain -domain_type {value} -domain_name {domain_name}

is_source_file_current

Audits the source file and determines whether or not the file is out of date / imported into the workspace. Returns '0' if file_name is out of date or has not been imported into the workspace, and returns '1' if file_name is current.

This command ignores the Audit settings in your ADB file.

is_source_file_current(filename)

get_defvar

get_defvar variable

Provides access to the internal variables within Designer and returns its value. This command also prints the value of the Designer variable on the Log window.

remove_min_delay

remove_min_delay [-from from_list] [-to to_list] [-through through_list] remove_min_delay -id constraint_ID

Removes a minimum delay constraint in the current timing scenario by specifying either its exact arguments or its ID.

new_design

new_design -name design_name -family family_name –path pathname–block value

Creates a new design. You need all three arguments for this command. This command will set up the Designer software for importing design source files

clone_scenario

clone_scenario name -source origin

Creates a new timing scenario by duplicating an existing one. You must provide a unique name (that is, it cannot already be used by another timing scenario).

smartpower_change_clock_statistics

Changes the default frequencies and probabilities for a specific domain.

smartpower_change_clock_statistics -domain_name {value} -clocks_freq {value} - clocks_proba {value} -registers_freq {value} -registers_proba {value} -set_reset_freq

{value} -set_reset_proba {value} -primaryinputs_freq {value} -primaryinputs_proba {value} - combinational_freq {value} -combinational_proba {value}

all_registers

Returns an object representing register pins or cells in the current scenario based on the given parameters.

all_registers [-clock clock_name]

[-async_pins][-output_pins][-data_pins][-clock_pins]

delete_files

Deletes files in your Libero IDE project.

delete_files

-file value

-from_disk

rename_library

Renames a VHDL library in your project.

rename_library

-library name

-name name

create_generated_clock

Tcl Command Documentation Conventions

remove_input_delay

remove_input_delay -clock clock_name port_pin_list

remove_input_delay -id constraint_ID

Removes an input delay a clock on a port by specifying both the clocks and port names or the ID of the input_delay constraint to remove.

st_create_set

Creates a set of paths to be analyzed. Use the arguments to specify which paths to include. To create a set that is a subset of a clock domain, specify it with -clock and -type. To create a set that is a subset of an inter-clock domain

set, specify it with -source_clock and -sink_clock. To create a set that is a subset (filter) of an existing named set, specify the set to be filtered with -from_set.

To create a set that is not derived from an existing set, you must provide both the -source pin_list and - sinkpin_list derived. Otherwise, the -source and -sink arguments act as filters on the pins from the parent set. You must give each new set a unique name in the design.

st_create_set -name name

[-parent_set name ]

[-clockclock_id -type value ] [-in_to_out]

[-source_clock clock_id -sink_clock clock_id] [-source pin_list ] -sink pin_list ]

remove_disable_timing

remove_disable_timing -from value -to value name -id name

Removes a disable timing constraint by specifying its arguments, or its ID. If the arguments do not match a disable timing constraint, or if the ID does not refer to a disable timing constraint, the command fails.

smartpower_remove_pin_probability

smartpower_remove_pin_probability –pin_name {pin_name}

Removes the probability value associated with a specific pin. This pin will have a default probability based on the domain set it belongs to.

get_design_filename

get_design_filename

Retrieves the full qualified path of the design file. The result will be an empty string if the design has not been saved to disk. This command is equivalent to the command “get_design_info DESIGN_PATH.” This command predates get_design_info and is supported for backward-compatibility.

timer_get_path_constraints

Displays the path constraints that were set as the maximum delay constraint in the timing analysis tool.

timer_get_path_constraints

save_design

save_design filename

The save_design command saves the current design in Designer to a file. If filename is not a complete path name, the ADB file is written into the current working directory.

timer_add_stop

Adds the specified pin to the list of pins through which the paths will not be displayed in the timing analysis tool.

timer_add_stop -pin pin_name

set_current_scenario

set_current_scenario name

Specifies the timing scenario for the Timing Analyzer to use. All commands that follow this command will apply to the specified timing scenario.

are_all_source_files_current

are_all_source_files_current

Audits all source files and determines whether or not they are out of date / imported into the workspace. Returns '1' if all source files are current Returns '0' if all source files are not current This command ignores the Audit settings in your ADB file.

smartpower_set_scenario_for_analysis

Sets the scenario for cycle-accurate power analysis.

smartpower_set_scenario_for_analysis -scenario{value}

smartpower_add_new_scenario

Creates a new scenario.

smartpower_add_new_scenario -name {value} -description {value} -mode {value}

remove_generated_clock

Removes the specified generated clock constraint from the current scenario.

remove_generated_clock {-name clock_name | -id constraint_ID }

smartpower_set_preferences

smartpower_set_preferences -powerunit {value} -frequnit {value} -opmode {value} -opcond

{value} -toggle {value}

Sets the following preferences: power unit, frequency unit, operating mode, operating conditions, and toggle. These preferences can also be set from the Preferences dialog box.

get_ports

Returns an object representing the port(s) that match those specified in the pattern argument.

get_portspattern

use_source_file

Defines a module for your project.

use_source_file

-file value

-module value

use_file

Specifies which file in your project to use.

use_file

-file value

-module value

-designer_view value

use_source_file

Defines a module for your project.

use_source_file

-file value

-module value

get_cells

Returns an object representing the cells (instances) that match those specified in the pattern argument.

get_cells pattern

st_edit_set

Modify the paths in a user set.

st_edit_set -name name

[-source pin_list ] [-sink pin_list ] [-rename_to name ]

list_output_delays

Returns details about all of the output delay constraints in the current timing constraint scenario.

list_output_delays

st_list_paths

Displays the list of paths in the same tabular format shown in SmartTime.

st_list_paths [-set name ]

[-clock clock_id -type value ] [-in_to_out]

[-source_clock clock_id -sink_clock clock_id] [-source pin_list ] [-sink pin_list ]

[-analysis value ] [-format value ]

generate_probes

generate_probes –save <ADB_file_name>

Executes the probing and creates a new ADB file. This command is used in conjunction with the add_probe Tcl command (see example below).

timer_commit

Saves the changes made to constraints into the Designer database.

timer_commit

set_design

set_design -name design_name -family family_name –pathpath_name

This set_design command specifies the design name, family and path in which Designer will process the design. This step is absolutely required before importing the source files.

You need all three arguments for this command to set up your design.

set_output_delay

Defines the output delay of an output relative to a clock in the current scenario.

set_output_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] output_list

st_set_options

st_set_options [-max_opcond value ] [-min_opcond value]

[-interclockdomain_analysis value] [-use_bibuf_loopbacks value]

[-enable_recovery_removal_checks value] [-break_at_async value]

[-filter_when_slack_below value] [-filter_when_slack_above value] [-remove_slack_filters]

[-limit_max_paths value]

[-expand_clock_network value] [-expand_parallel_paths value] [-analysis_scenario value]

[-tdpr_scenario value] [-reset]

Sets options for timing analysis. With no parameters given, it will display the current settings of the options. For IGLOO, ProASIC3, SmartFusion, Fusion, ProASIC^PLUS, and Axcelerator families, these options also affect timing-driven place-and-route.

set_defvar

set_defvar variable value

The set_defvar command sets an internal variable in the Designer system. You must specify at least one argument for this command.

timer_add_clock_exception

Adds an exception to or from a pin with respect to a specified clock.

timer_add_clock_exception -clock clock_name -pin pin_name -dir value

smartpower_edit_custom_mode

Edits a custom mode.

smartpower_edit_custom_mode -name {old_mode_name} new_name {new_mode_name} -description

{mode_description}

remove_clock_uncertainty

remove_clock_uncertainty -from | -rise_from | -fall_from from_clock_list -to | -rise_to| - fall_to to_clock_list -setup {value} -hold {value}

remove_clock_uncertainty -id constraint_ID

Removes a clock-to-clock uncertainty from the current timing scenario by specifying either its exact arguments or its ID.

create_generated_clock

Creates an internally generated clock constraint on the ports/pins and defines its characteristics.

create_generated_clock [-name name] -source reference_pin [-divide_by divide_factor] [-multiply_by multiply_factor] [-invert] source

remove_clock_latency

Removes a clock source latency from the specified clock and from all edges of the clock.

remove_clock_latency {-source clock_name_or_source |-id constraint_ID}

smartpower_remove_scenario

Remmoves a scenario from the current design.

smartpower_remove_scenario -name {value}

add_probe

Adds a probe to an internal net in your design, using the original name from the optimized netlist in your design. Also, this command must be used in conjunction with the generate_probes command to generate a probed ADB file (see example below).

You must complete layout before you use this command.

add_probe –net <net_name> [-pin <pin_name>] [-port <port_name>] [-assign_to_used_pin

<TRUE|FALSE>]

st_remove_set

Deletes a user set from the design.

st_remove_set -name name