3.4.3.8.1.3 RDSIFR – RX DSP Status
Interrupt Flag Register
| Name: | RDSIFR |
| Offset: | 0x00D |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WCOB | WCOA | SOTB | SOTA | EOTB | EOTA | NBITB | NBITA | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – WCOB Wake Check OK on
Path B
Set if the receiving path B is
enabled (RDCR.RDEN = 1, RDPR.PRFLT = 0, RDPR.PRPTB
= 0) and all start of telegram conditions that are configured in
the SOTCB[7:6] and SOTCB[4:0] register are true. The SFID condition SOTCB[5] is
ignored for the WCOB interrupt. It is automatically cleared when the corresponding
interrupt is executed or it can be cleared by writing a ‘1’ to its
bit location. This interrupt is a reduced version of the SOTB interrupt allowing
some actions to be started before the SFIDB match occurs. Its conditions can also be
used to enable the TMDO output if configured accordingly.
Bit 6 – WCOA Wake Check OK on
Path A
Set if the receiving path A is
enabled (RDCR.RDEN = 1, RDPR.PRFLT = 0, RDPR.PRPTA
= 0) and all start of telegram conditions that are configured in
the SOTCA[7:6] and SOTCA[4:0] register are true. The SFID condition SOTCA[5] is
ignored for the WCOA interrupt. It is automatically cleared when the corresponding
interrupt is executed or it can be cleared by writing a ‘1’ to its
bit location. This interrupt is a reduced version of the SOTA interrupt allowing
some actions to be started before the SFIDA match occurs. Its conditions can also be
used to enable the TMDO output if configured accordingly.
Bit 5 – SOTB Start Of Telegram
on Path B
Set if the receiving path B is
enabled (RDCR.RDEN = 1, RDPR.PRFLT = 0, RDPR.PRPTB
= 0) and all start of telegram conditions that are configured in
the STOCB register are true. It is automatically cleared when the corresponding
interrupt is executed or it can be cleared by writing a ‘1’ to its
bit location.
Bit 4 – SOTA Start Of Telegram
on Path A
Set if the receiving path A is
enabled (RDCR.RDEN = 1, RDPR.PRFLT = 0, RDPR.PRPTA
= 0) and all start of telegram conditions that are configured in
the SOTCA register are true. It is automatically cleared when the corresponding
interrupt is executed or it can be cleared by writing a ‘1’ to its
bit location.
Bit 3 – EOTB End of Telegram on
Path B
Set if at least one end of
telegram condition configured in EOTCB is true. It is automatically cleared when the
corresponding interrupt is executed or it can be cleared by writing a
‘1’ to the EOTB bit location. Writing a ‘1’ to
the EOTB bit location also clears all EOTSB flags.
Bit 2 – EOTA End of Telegram on
Path A
Set if at least one end of
telegram condition configured in EOTCA is true. It is automatically cleared when the
corresponding interrupt is executed or it can be cleared by writing a
‘1’ to the EOTA bit location. Writing a ‘1’ to
the EOTA bit location also clears all EOTSA flags.
Bit 1 – NBITB New Bit on RX Path
B
Set if a new bit is received
on data path B. It is automatically cleared when the corresponding interrupt is
executed or it can be cleared by writing a ‘1’ to its bit
location.
Bit 0 – NBITA New Bit on RX Path
A
Set if a new bit is received
on data path A. It is automatically cleared when the corresponding interrupt is
executed or it can be cleared by writing a ‘1’ to its bit
location.
