3.4.3.8.1.23 TESRA –
Telegram Status Register on Path A
| Name: | TESRA |
| Offset: | 0x096 |
| Reset: | 0x00 |
This is
the status register for path A. It provides additional information compared to the EOTSA
register but it cannot be used for an automatic restart of path
A.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | EOTLA[1:0] | CRCOA | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and
returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 4 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bits 2:1 – EOTLA[1:0] End of Telegram
Location on Path A
If the get_rx_telegram state
machine is activated (SSMRR.SSMR = 1), these two bits indicate the
location of the EOTA event within the telegram. These bits are not cleared when the
get_rx_telegram state machine is disabled (SSMRR.SSMR = 0).
Table 3-37. EOTLA Bit Setting
versus EOTA Location| EOTLA1 | EOTLA0 | Description |
|---|
0 | 0 | No EOTA |
0 | 1 | Before WCOA |
1 | 0 | Between WCOA and SOTA |
1 | 1 | After SOTA |
Bit 0 – CRCOA Cyclic Redundancy
Check OK on Path A
This bit is set when a
telegram is received without CRC error on path A. This bit is cleared when the RX
buffer is disabled (PRR2.PRXB = 1) and enabled (PRR2.PRXB =
0) again or when the RX buffer is cleared (RXBC2.RXBCLR =
1).
