3.4.3.8.1.25 TESRB –
Telegram Status Register on Path B
| Name: | TESRB |
| Offset: | 0x095 |
| Reset: | 0x00 |
This is
the status register for path B. It provides additional information compared to the EOTSB
register but it cannot be used for an automatic restart of the path
B.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | EOTLB[1:0] | CRCOB | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and
returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 4 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
returns ‘0’ when read.
Bits 2:1 – EOTLB[1:0] End of Telegram
Location on Path B
If the get_rx_telegram state
machine is activated (SSMRR.SSMR = 1), these two bits indicate the
location of the EOTB event within the telegram. These bits are not cleared when the
get_rx_telegram state machine is disabled (SSMRR.SSMR = 0).
Table 3-38. EOTLB Bit Setting
versus EOTB Location| EOTLB1 | EOTLB0 | Description |
|---|
0 | 0 | No EOTB |
0 | 1 | Before WCOB |
1 | 0 | Between WCOB and SOTB |
1 | 1 | After SOTB |
Bit 0 – CRCOB Cyclic Redundancy
Check OK on Path B
This bit is set when a
telegram is received without a CRC error on path B. This bit is cleared when the RX
buffer is disabled (PRR2.PRXB = 1) and enabled (PRR2.PRXB =
0) again or when the RX buffer is cleared (RXBC2.RXBCLR =
1).
