3.4.3.8.1.7 SOTC1A – Start
of Telegram Conditions 1 for Path A
This register is used
only for hardware-controlled automatic telegram reception. It stores the SOTCA settings
that are valid from the start of the reception until a wake check OK (RDSIFR.WCOA) is
detected. The sequencer state machine copies its content to the SOTCA register at the
beginning of reception.Note: The bit descriptions are found at the SOTCA target
register.
| Name: | SOTC1A |
| Offset: | 0x0F1 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WCOBOE | RROEA | SFIDEA | WUPEA | MANOEA | SYTOEA | AMPOEA | CAROEA | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 7 – WCOBOE
Bit 6 – RROEA
Bit 5 – SFIDEA
Bit 4 – WUPEA
Bit 3 – MANOEA
Bit 2 – SYTOEA
Bit 1 – AMPOEA
Bit 0 – CAROEA
