3.4.3.8.1.12 SOTSA – Start Of Telegram Status for Path A

Note:

Set to hardware-controlled read-only mode if the get_rx_telegram state machine is active.

Name:	SOTSA
Offset:	0x092
Reset:	0x00

This register displays the status of all start of telegram conditions. The corresponding bit is set to ‘1’ if the condition has matched. It is cleared if a ‘1’ is written to its position or the receiving path A is disabled (RDPR.PRFLT = 1 or RDPR.PRPTA = 1). The flags are handled by the hardware if the get_rx_telegram state machine is activated (SSMRR.SSMR). In this case, the flags are cleared if an activated error condition for RDSIFR.EOTA occurs. This is done automatically by toggling the RDPR.APRPTA bit.


Bit	7	6	5	4	3	2	1	0
	WCOBO	RROA	SFIDOA	WUPOA	MANOA	SYTOA	AMPOA	CAROA
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – WCOBO Wake Check OK on Path B OK

The bit is set at a successful wake check OK from path B (RDSIFR.WCOB) that can be used as a precondition for a successful wake check (RDSIFR.WCOA) and start of telegram (RDSIFR.SOTA) detection on path A. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 6 – RROA RSSI Range OK on Path A

This bit is set if the received signal strength on path A is within the expected range. The RSSI comparison is based on the first averaged RSSI sample after RX start-up. A failure of this check is indicated by the setting of the RSSFA flag in the EOTSA register. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 5 – SFIDOA Start of Frame Identifier Matched on Path A

This bit indicates a successful correlator-based start of frame ID check. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 4 – WUPOA Wake-Up Pattern Matched on Path A

This bit is set if the wake-up pattern match occurred. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 3 – MANOA Manchester Coding OK on Path A

This bit is set if the Manchester coding check is OK. The Manchester coding is verified for the duration specified in the SYCSA register. If it was right for this duration, it is considered OK. A failure of this check is indicated by the setting of the MANFEA flag in the EOTS register. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 2 – SYTOA Symbol Timing OK on Path A

This bit is set if the symbol timing check is OK. The symbol timing is verified for the duration specified in the SYCSA register. If it was right for this duration, it is considered OK. A failure of this check is indicated by the setting of the SYTFEA flag in the EOTS register. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 1 – AMPOA Amplitude OK on Path A

This bit is set if the signal amplitude inside the demodulator is above a specified threshold (DMMA.DMATA). A failure of this check is indicated by the setting of the AMPFA flag in the EOTSA register. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.

Bit 0 – CAROA Carrier Check OK on Path A

This bit is set by a successful signal carrier check. A failure of this check is indicated by the setting of the CARFA flag in the EOTSA register. It is cleared if a ‘1’ is written to its position, a ‘1’ is written to the RDSIFR.SOTA interrupt flag, or the receiving path A is disabled.