3.4.3.8.1.4 RDSIMR – RX DSP
Status Interrupt Mask Register
| Name: | RDSIMR |
| Offset: | 0x098 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WCOBM | WCOAM | SOTBM | SOTAM | EOTBM | EOTAM | NBITBM | NBITAM | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – WCOBM Wake Check OK on
Path B Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.WCOB flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the WCOB bit in RDSIFR is set.
Bit 6 – WCOAM Wake Check OK on
Path A Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.WCOA flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the WCOA bit in RDSIFR is set.
Bit 5 – SOTBM Start Of Telegram
on RX Path B Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.SOTB flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the SOTB bit in RDSIFR is set.
Bit 4 – SOTAM Start Of Telegram
on RX Path A Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.SOTA flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the SOTA bit in RDSIFR is set.
Bit 3 – EOTBM End Of Telegram on
RX Path B Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.EOTB flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the EOTB bit in RDSIFR is set.
Bit 2 – EOTAM End Of Telegram on
RX Path A Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.EOTA flag. An interrupt
is generated only if this bit is HIGH, the global interrupt flag in the SREG is
activated and the EOTA bit in RDSIFR is set.
Bit 1 – NBITBM New Bit on RX Path
B Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.NBITB flag. An
interrupt is generated only if this bit is HIGH, the global interrupt flag in the
SREG is activated and the NBITB bit in RDSIFR is set.
Bit 0 – NBITAM New Bit on RX Path
A Interrupt Mask Register
Writing this bit to
‘1’ enables the interrupt on the RDSIFR.NBITA flag. An
interrupt is generated only if this bit is HIGH, the global interrupt flag in the
SREG is activated and the NBITA bit in RDSIFR is set.
