3.4.3.8.1.10 SOTC1B – Start
of Telegram Conditions 1 for Path B
This register is used
only for hardware-controlled automatic telegram reception. It stores the SOTCB settings
that are valid from the start of the reception until a wake check OK (RDSIFR.WCOB) is
detected. The sequencer state machine copies its content at the beginning of the
reception to the SOTCB register.
Note: The bit descriptions are found at the SOTCB target
register.
Name:
SOTC1B
Offset:
0x0F3
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
WCOAOE
RROEB
SFIDEB
WUPEB
MANOEB
SYTOEB
AMPOEB
CAROEB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit 7 – WCOAOE
Bit 6 – RROEB
Bit 5 – SFIDEB
Bit 4 – WUPEB
Bit 3 – MANOEB
Bit 2 – SYTOEB
Bit 1 – AMPOEB
Bit 0 – CAROEB
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
