3.4.3.8.1.1 RDCR – RX DSP Control Register
Note:
- Writable only if RDCR.RDEN =
0.
| Name: | RDCR |
| Offset: | 0x033 |
| Reset: | 0x00 |
Controls the operation of the RX DSP block
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDEN | ADIVEN | RDPU | |||||||
| Access | R | R | R | R | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – Reserved Bit
0’ when read.Bit 6 – Reserved Bit
0’ when read.Bit 5 – Reserved Bit
0’ when read.Bit 3 – Reserved Bit
0’ when read.Bit 2 – RDEN RX DSP Enable
| Value | Description |
|---|---|
0 |
RxDSP is disabled, all RX DSP registers are in the
asynchronous reset state. The power reduction bits for the
RxDSP are set to ‘ |
1 | RxDSP is enabled with some delay to assure synchronous operation. Some clock dividers are running to allow the setting of configuration data. The channel filter and the demodulator have to be enabled separately by clearing the corresponding power reduction registers (RDPR.PRFLT, RDPR.PRPTA/B, PRR2.PRXA/B). |
Bit 1 – ADIVEN Divided ADC Clock Enable
CAUTION: This bit can only be modified while RDCR.RDEN =
0. A clock is
generated if the ADC is running, and the RX DSP is enabled (RDCR.RDEN =
1) because this is the clock source for the
generator.| Value | Description |
|---|---|
0 | Divided ADC clock output is disabled. |
1 | Divided ADC clock output is enabled. |