3.4.3.8.1.22 EOTSA – End of
Telegram Status on Path A
This is the status
register for the EOT conditions on path A. The RDSIFR.EOTA interrupt flag is set if one
of the fail conditions selected in the EOTCA register becomes true in the EOTSA
register. The bits in the EOTSA register are set if the corresponding fail condition is
detected on the RX path A. The flags are handled by the hardware if the get_rx_telegram
state machine is activated (SSMRR.SSMR). In this case, the flags are cleared if an
activated error condition for RDSIFR.EOTA occurs. This is done automatically by toggling
the RDPR.APRPTA bit.
Note:
- Set R/W access to
hardware-controlled read-only mode if the get_rx_telegram state machine
is active.
| Name: | EOTSA |
| Offset: | 0x034 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | EOTBF | RRFA | TELRA | TMOFA | MANFA | SYTFA | AMPFA | CARFA | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – EOTBF End Of Telegram on
Path B Flag
The bit is set to
‘1’ simultaneously with the RDSIFR.EOTB interrupt flag
register. It can be used to set the RDSIFR.EOTA flag based on RDSIFR.EOTB, allowing
both paths to be restarted simultaneously. This is useful when the start of telegram
condition on path A depends on the wake check OK (RDSIFR.WCOB) of path B. It is
cleared if a ‘1’ is written to its position, a ‘1’
is written to the RDSIFR.EOTA interrupt flag, a new value is written to the EOTCA
register, or the receiving path A is disabled.
Bit 6 – RRFA RSSI Range Fail on
Path A
This bit is set if the
received signal strength on path A is within the expected range. It is cleared if a
‘1’ is written to its position, a ‘1’ is
written to the RDSIFR.EOTA interrupt flag, a new value is written to the EOTCA
register or the receiving path A is disabled.
Bit 5 – TELRA Telegram Length
Reached on Path A
This bit is set if the target
telegram length is reached on path A. It is cleared if a ‘1’ is
written to its position, a ‘1’ is written to the RDSIFR.EOTA
interrupt flag, a new value is written to the EOTCA register, or the receiving path
A is disabled.
Bit 4 – TMOFA Time-out Fail on
Path A
This bit is set to
‘1’ if a time-out occurs during wake check OK search on path A
or during start of telegram search on path A. For the time-out duration see the
description of the corresponding sequencer state machine registers. Each time-out
can be deactivated by setting the duration to ‘0’. It is cleared if
a ‘1’ is written to its position, a ‘1’ is written
to the RDSIFR.EOTA interrupt flag, a new value is written to the EOTCA register or
the receiving path A is disabled.
Bit 3 – MANFA Manchester Coding
Failed on Path A
This bit is set if the
Manchester coding check failed on path A. It is cleared if a ‘1’ is
written to its position, a ‘1’ is written to the RDSIFR.EOTA
interrupt flag, a new value is written to the EOTCA register or the receiving path A
is disabled.
Bit 2 – SYTFA Symbol Timing Check
Failed on Path A
This bit is set if the symbol
timing check failed on path A. It is cleared if a ‘1’ is written to
its position, a ‘1’ is written to the RDSIFR.EOTA interrupt flag, a
new value is written to the EOTCA register or the receiving path A is
disabled.
Bit 1 – AMPFA Amplitude Check
Failed on Path A
This bit is set if the
demodulator amplitude check failed on path A. It is cleared if a
‘1’ is written to its position, a ‘1’ is written
to the RDSIFR.EOTA interrupt flag, a new value is written to the EOTCA register or
the receiving path A is disabled.
Bit 0 – CARFA Carrier Check
Failed on Path A
This bit is set if the carrier
check failed on path A. It is cleared if a ‘1’ is written to its
position, a ‘1’ is written to the RDSIFR.EOTA interrupt flag, a new
value is written to the EOTCA register or the receiving path A is
disabled.
