7.7.26 Interrupt Priority Register 5
| Name: | IPC5 |
| Offset: | 0x84A |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CCP2IP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMA3IP[6:4] | INT2IP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | |||
Bits 14:12 – CCP2IP[2:0] Interrupt-on-Change 2 Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 6:4 – DMA3IP[6:4] Direct Memory Access 3 Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 2:0 – INT2IP[2:0] External Interrupt 2 Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |