7.7 Status/Control Registers

Although these registers are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. For more information on these registers, refer to “Enhanced CPU” (www.microchip.com/DS70005158) in the “dsPIC33/PIC24 Family Reference Manual”.

  • The CPU STATUS Register, SR, contains the IPL[2:0] bits (SR[7:5]). These bits indicate the current CPU Interrupt Priority Level. The user software can change the current CPU Interrupt Priority Level by writing to the IPLx bits.
  • The CORCON register contains the IPL3 bit, which together with IPL[2:0], also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software.
OffsetNameBit Pos.76543210
0x0800IFS015:8INT1IFNVMIFECCSBEIFU1TXIFU1RXIFSPI1TXIFSPI1RXIFDMA1IF
7:0CCT1IFCCP1IF DMA0IFCNBIFCNAIFT1IFINT0IF
0x0802IFS115:8C1RXIFSPI2TXIFSPI2RXIFU2TXIFU2RXIFINT3IFC1IFCCT2IF
7:0CCP2IF DMA3IFINT2IFCNCIFDMAIFMI2C1IFSI2C1IF
0x0804IFS215:8  DMTIF   CCT4IFCCP4IF
7:0   CCT3IFCCP3IF   
0x0806IFS315:8PTGSTEPIF ICDIF  U3TXIFU3RXIFU3EIF
7:0   C1TXIFCRCIFU2EIFU1EIF 
0x0808IFS415:8  CMP1IF CNDIF   
7:0 PWM4IFPWM3IFPWM2IFPWM1IF  I2C1BCIF
0x080AIFS515:8AD1AN4IFAD1AN3IFAD1AN2IFAD1AN1IFAD1AN0IFADCIF  
7:0SENT1EIFSENT1IFPTG3IFPTG2IFPTG1IFPTG0IFPTGWDTIF 
0x080CIFS615:8AD1AN20IFAD1AN19IFAD1AN18IFAD1AN17IFAD1AN16IFAD1AN15IFAD1AN14IFAD1AN13IF
7:0AD1AN12IFAD1AN11IFAD1AN10IFAD1AN9IFAD1AN8IFAD1AN7IFAD1AN6IFAD1AN5IF
0x080EIFS715:8SPI2IFSPI1IFCLC2PIFCLC1PIFADFLTR3IFADFLTR2IFADFLTR1IFADFLTR0F
7:0ADCMP3IFADCMP2IFADCMP1IFADCMP0IF   AD1AN21IF

0x0810

...

0x0813

Reserved         
0x0814IFS1015:8CLC3PIFPEVTFIFPEVTEIFPEVTDIFPEVTCIFPEVTBIFPEVTAIF 
7:0      ADCC1EIFADCC0EIF
0x0816IFS1115:8U3ENTIFU2ENTIFU1ENTIF     
7:0   CLC4NIFCLC3NIFCLC2NIFCLC1NIFCLC4PIF

0x0818

...

0x081F

Reserved         
0x0820IEC015:8INT1IENVMIEECCSBEIEU1TXIEU1RXIESPI1TXIESPI1RXIEDMA1IE
7:0CCT1IECCP1IE DMA0IECNBIECNAIET1IEINT0IE
0x0822IEC115:8C1RXIESPI2TXIESPI2RXIEU2TXIEU2RXIEINT3IEC1IECCT2IE
7:0CCP2IE DMA3IEINT2IECNCIEDMA2IEMI2C1IESI2C1IE
0x0824IEC215:8  DMTIE   CCT4IECCP4IE
7:0   CCT3IECCP3IE   
0x0826IEC315:8PTGSTEPIE ICDIE  U3TXIEU3RXIEU3EIE
7:0   C1TXIECRCIEU2EIEU1EIE 
0x0828IEC415:8  CMP1IE CNDIE   
7:0 PWM4IEPWM3IEPWM2IEPWM1IE  I2C1BCIE
0x082AIEC515:8AD1AN4IEAD1AN3IEAD1AN2IEAD1AN1IEAD1AN0IEADCIE  
7:0SENT1EIESENT1IEPTG3IEPTG2IEPTG1IEPTG0IEPTGWDTIE 
0x082CIEC615:8AD1AN20IEAD1AN19IEAD1AN18IEAD1AN17IEAD1AN16IEAD1AN15IEAD1AN14IEAD1AN13IE
7:0AD1AN12IEAD1AN11IEAD1AN10IEAD1AN9IEAD1AN8IEAD1AN7IEAD1AN6IEAD1AN5IE
0x082EIEC715:8SPI2GIESPI1GIECLC2PIECLC1PIEADFLTR3IEADFLTR2IEADFLTR1IEADFLTR0IE
7:0ADCMP3IEADCMP2IEADCMP1IEADCMP0IE   AD1AN21IE

0x0830

...

0x0833

Reserved         
0x0834IEC1015:8CLC3PIEPEVTFIEPEVTEIEPEVTDIEPEVTCIEPEVTBIEPEVTAIE 
7:0        
0x0836IEC1115:8U3ENTIEU2ENTIEU1ENTIE     
7:0   CLC4NIECLC3NIECLC2NIECLC1NIECLC4PIE

0x0838

...

0x083F

Reserved         
0x0840IPC015:8 CNBIP[2:0] CNAIP[2:0]
7:0 T1IP[2:0] INT0IP[2:0]
0x0842IPC115:8 CCT1IP[2:0] CCP1IP[2:0]
7:0     DMA0IP[2:0]
0x0844IPC215:8 U1RXIP[2:0] SPI1TXIP[2:0]
7:0 SPI1RXIP[2:0] DMA1IP[2:0]
0x0846IPC315:8 INT1IP[2:0] NVMIP[2:0]
7:0 ECCSBIP[2:0] U1TXIP[2:0]
0x0848IPC415:8 CNCIP[2:0] DMA2IP[2:0]
7:0 MI2C1IP[2:0] SI2C1IP[2:0]
0x084AIPC515:8 CCP2IP[2:0]    
7:0 DMA3IP[6:4] INT2IP[2:0]
0x084CIPC615:8 U2RXIP[2:0] INT3IP[2:0]
7:0 C1IP[2:0] CCT2IP[2:0]
0x084EIPC715:8 C1RXIP[2:0] SPI2TXIP[2:0]
7:0 SPI2RXIP[2:0] U2TXIP[2:0]
0x0850IPC815:8 CCP3IP[2:0]    
7:0        
0x0852IPC915:8        
7:0     CCT3IP[2:0]
0x0854IPC1015:8        
7:0 CCT4IP[2:0] CCP4IP[2:0]
0x0856IPC1115:8        
7:0 DMTIP[2:0]    
0x0858IPC1215:8 CRCIP[2:0] U2EIP[2:0]
7:0 U1EIP[2:0]    
0x085AIPC1315:8        
7:0     C1TXIP[2:0]
0x085CIPC1415:8     U3TXIP[2:0]
7:0 U3RXIP[2:0] U3EIP[2:0]
0x085EIPC1515:8 PTGSTEPIP[2:0]    
7:0 ICDIP[2:0]    
0x0860IPC1615:8 PWM1IP[2:0]    
7:0     I2C1BCIP[2:0]
0x0862IPC1715:8     PWM4IP[2:0]
7:0 PWM3IP[2:0] PWM2IP[2:0]
0x0864IPC1815:8 CNDIP[2:0]    
7:0        
0x0866IPC1915:8        
7:0 CMP1IP[2:0]    
0x0868IPC2015:8 PTG1IP[2:0] PTG0IP[2:0]
7:0 PTGWDTIP[2:0]    
0x086AIPC2115:8 SENT1EIP[2:0] SENT1IP[2:0]
7:0 PTG3IP[2:0] PTG2IP[2:0]
0x086CIPC2215:8 AD1AN0IP[2:0] ADCIP[2:0]
7:0        
0x086EIPC2315:8 AD1AN4IP[2:0] AD1AN3IP[2:0]
7:0 AD1AN2IP[2:0] ADCAN1IP[2:0]
0x0870IPC2415:8 AD1AN8IP[2:0] AD1AN7IP[2:0]
7:0 AD1AN6IP[2:0] AD1AN5IP[2:0]
0x0872IPC2515:8 AD1AN12IP[2:0] AD1AN11IP[2:0]
7:0 AD1AN10IP[2:0] AD1AN9IP[2:0]
0x0874IPC2615:8 AD1AN16IP[2:0] AD1AN15IP[2:0]
7:0 AD1AN14IP[2:0] AD1AN13IP[2:0]
0x0876IPC2715:8 AD1AN20IP[2:0] AD1AN19IP[2:0]
7:0 AD1AN18IP[2:0] AD1AN17IP[2:0]
0x0878IPC2815:8        
7:0     AD1AN21IP[2:0]
0x087AIPC2915:8 ADCMP3IP[2:0] ADCMP2IP[2:0]
7:0 ADCMP1IP[2:0] ADCMP0IP[2:0]
0x087CIPC3015:8 ADFLTR3IP[2:0] ADFLTR2IP[2:0]
7:0 ADFLTR1IP[2:0] ADFLTR0IP[2:0]
0x087EIPC3115:8 SPI2IP[2:0] SPI1IP[2:0]
7:0 CLC2PIP[2:0] CLC1PIP[2:0]

0x0880

...

0x0893

Reserved         
0x0894IPC4215:8 PEVTCIP[2:0] PEVTBIP[2:0]
7:0 PEVTAIP[2:0]    
0x0896IPC4315:8 CLC3PEIP[2:0] PEVTFIP[2:0]
7:0 PEVTEIP[2:0] PEVTDIP[2:0]
0x0898IPC4415:8 CLC3NEIP[2:0] CLC2NEIP[2:0]
7:0 CLC1NEIP[2:0] CLC4PEIP[2:0]
0x089AIPC4515:8        
7:0     CLC4NEIP[2:0]

0x089C

...

0x089D

Reserved         
0x089EIPC4715:8 U3EVTIP[2:0] U2EVTIP[2:0]
7:0 U1EVTIP[2:0]    

0x08A0

...

0x08BF

Reserved         
0x08C0INTCON115:8NSTDISOVAERROVBERRCOVAERRCOVBERROVATEOVBTECOVTE
7:0SFTACERRDIV0ERR MATHERRADDRERRSTKERROSCFAIL 
0x08C2INTCON215:8GIEDISISWTRAP    AIVTEN
7:0    INT3EPINT2EPINT1EPINT0EP
0x08C4INTCON315:8      CANNAE
7:0  DAEDOOVR    
0x08C6INTCON415:8        
7:0      ECCDBESGHT
0x08C8INTTREG15:8  VHOLD ILR[3:0]
7:0VECNUM[7:0]