46.10.1 System Clock

Table 46-9. System Clock Timing Characteristics
Symbol	Description	Min.	Typ. ✝	Max.	Units
f_{CLK_MAIN}	Main clock frequency^(1,2)			20	MHz
f_CY	Instruction clock frequency		f_{CLK_MAIN}		MHz
T_CY	Instruction period⁽³⁾	50	1/f_CY		ns
✝ Unless otherwise specified, data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V. These parameters are not tested and are for design guidance only. Note: The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section. The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in the Standard Operating Conditions section. Instruction Cycle Period (T_CY) equals the input oscillator time base period. Exceeding these limits may result in incorrect code execution and/or higher-than-expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.